283 lines
8.3 KiB
Python
283 lines
8.3 KiB
Python
# ---------------------------------------------------------
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# Simulateur
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# ---------------------------------------------------------
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# - Bus données : 8 bits
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# - 4 registres R0..R3 (8 bits)
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# - Bus adresse : 8 bits
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# - RAM : 256 octets
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# - Instructions : 1 ou 2 octets
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# - Cycles : 1 octet -> 1, 2 octets -> 2, LDR/STR -> 3
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# - PC démarre à 0
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# - Pile descendante, SP=255
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# ---------------------------------------------------------
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from dataclasses import dataclass, field
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import sys
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@dataclass
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class CPU:
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pc: int = 0
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sp: int = 255
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regs: list = field(default_factory=list) # R0..R3
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lt: int = 0 # flag LT
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eq: int = 0 # flag EQ
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cycles: int = 0
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running: bool = True
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after_ret: bool = False
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last_out = None
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def __post_init__(self):
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if not self.regs:
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self.regs = [0, 0, 0, 0]
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class Simulator:
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cycles_added = 0
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def __init__(self, program: bytes):
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self.ram = bytearray(256)
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for i, b in enumerate(program[:256]):
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self.ram[i] = b
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self.cpu = CPU()
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self.program_size = len(program)
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# ----------------- utilitaires mémoire / pile -----------------
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def fetch_byte(self) -> int:
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b = self.ram[self.cpu.pc]
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self.cpu.pc = (self.cpu.pc + 1) & 0xFF
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return b
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def push(self, value: int):
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if self.cpu.sp < 0:
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raise RuntimeError("STACK OVERFLOW")
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self.ram[self.cpu.sp] = value & 0xFF
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self.cpu.sp -= 1
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def pop(self) -> int:
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if self.cpu.sp >= 255:
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return 0
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self.cpu.sp += 1
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return self.ram[self.cpu.sp]
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# ----------------- exécution d'une instruction -----------------
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def step(self):
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c = self.cpu
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pc_before = c.pc
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b = self.fetch_byte()
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instr = ""
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size = 1 # taille en octets (1 ou 2)
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extra_cycles = 0 # pour LDR/STR/TIM
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if b == 0x00: # CALL _label
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addr = self.fetch_byte()
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size = 2
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instr = f"CALL {addr}"
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self.push(c.pc)
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c.pc = addr
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elif b == 0x40: # JMP _label
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addr = self.fetch_byte()
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size = 2
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instr = f"JMP {addr}"
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c.pc = addr
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elif b == 0xC0: # JLT _label
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addr = self.fetch_byte()
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size = 2
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instr = f"JLT {addr}"
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if c.lt == 1:
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c.pc = addr
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elif b == 0x20: # JEQ _label
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addr = self.fetch_byte()
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size = 2
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instr = f"JEQ {addr}"
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if c.eq == 1:
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c.pc = addr
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elif b == 0x80: # RET
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instr = "RET"
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ret = self.pop()
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if c.sp >= 255 and ret == 0:
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c.after_ret = True
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c.running = False
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else:
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c.pc = ret
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# --- PUSH / POP ---
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elif (b & 0b11111100) == 0b10100000: # PUSH Rx
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r = b & 0b11
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instr = f"PUSH R{r}"
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self.push(c.regs[r])
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elif (b & 0b11111100) == 0b01100000: # POP Rx
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r = b & 0b11
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instr = f"POP R{r}"
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c.regs[r] = self.pop()
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# --- MOV Rx valeur / SUB Rx valeur / CMP Rx valeur ---
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elif (b & 0b11111100) == 0b11100000: # MOV Rx valeur
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r = b & 0b11
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imm = self.fetch_byte()
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size = 2
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instr = f"MOV R{r}, {imm}"
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c.regs[r] = imm
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elif (b & 0b11111100) == 0b00010000: # SUB Rx valeur
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r = b & 0b11
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imm = self.fetch_byte()
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size = 2
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instr = f"SUB R{r}, {imm}"
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c.regs[r] = (c.regs[r] - imm) & 0xFF
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elif (b & 0b11111100) == 0b10010000: # CMP Rx valeur
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r = b & 0b11
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imm = self.fetch_byte()
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size = 2
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instr = f"CMP R{r}, {imm}"
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v = c.regs[r]
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c.lt = 1 if v < imm else 0
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c.eq = 1 if v == imm else 0
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# --- MOV / SUB / CMP registre-registre ---
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elif (b & 0b11110000) == 0b01010000: # MOV Rx Ry
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dst = (b >> 2) & 0b11
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src = b & 0b11
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instr = f"MOV R{dst}, R{src}"
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c.regs[dst] = c.regs[src]
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elif (b & 0b11110000) == 0b11010000: # SUB Rx Ry
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dst = (b >> 2) & 0b11
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src = b & 0b11
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instr = f"SUB R{dst}, R{src}"
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c.regs[dst] = (c.regs[dst] - c.regs[src]) & 0xFF
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elif (b & 0b11110000) == 0b00110000: # CMP Rx Ry
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dst = (b >> 2) & 0b11
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src = b & 0b11
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instr = f"CMP R{dst}, R{src}"
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v1 = c.regs[dst]
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v2 = c.regs[src]
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c.lt = 1 if v1 < v2 else 0
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c.eq = 1 if v1 == v2 else 0
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# --- LDR / STR (2 octets, 3 cycles) ---
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elif (b & 0b11110000) == 0b10110000: # LDR Rx Ry _label
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dst = (b >> 2) & 0b11
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src = b & 0b11
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addr = self.fetch_byte()
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size = 2
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instr = f"LDR R{dst}, R{src}, {addr}"
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eff = (addr + c.regs[src]) & 0xFF
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c.regs[dst] = self.ram[eff]
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extra_cycles = 1 # 2 octets -> 2 cycles +1 = 3
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elif (b & 0b11110000) == 0b01110000: # STR Rx Ry _label
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dst = (b >> 2) & 0b11
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src = b & 0b11
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addr = self.fetch_byte()
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size = 2
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instr = f"STR R{dst}, R{src}, {addr}"
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eff = (addr + c.regs[src]) & 0xFF
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self.ram[eff] = c.regs[dst] & 0xFF
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extra_cycles = 1
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# --- OUT Rx ---
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elif (b & 0b11111100) == 0b11110000: # OUT Rx
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r = b & 0b11
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instr = f"OUT R{r}"
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print(f"[OUT] R{r} = {c.regs[r]}")
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self.cpu.last_out = c.regs[r]
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# --- TIM valeur ---
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elif b == 0xF8: # TIM
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second = self.fetch_byte()
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size = 2
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m = (second >> 7) & 0x1
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v = second & 0x7F
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instr = f"TIM m={m}, v={v}"
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mult = 1 if m == 0 else 100
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pause_ms = mult * (v + 1)
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c.cycles += pause_ms # modélisation de la pause
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else: # Si DB est apres RET on n atteind pas ce bloc
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instr = f"DB 0x{b:02X}"
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size = 0 # DB n'est pas une INS
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# instr = f"UNKNOWN 0x{b:02X}"
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# c.running = False
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# calcul des cycles
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if (b & 0b11110000) in (0xB0, 0x70): # LDR / STR
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c.cycles += 3
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cycles_added = 3
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else:
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c.cycles += size
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cycles_added = size
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return self.report(pc_before, instr, cycles_added)
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# ----------------- rapport d'exécution -----------------
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def report(self, pc_before: int, instr: str, cycles_added: int):
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c = self.cpu
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regs_str = " ".join(f"R{i}={c.regs[i]:02X}" for i in range(4))
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print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}")
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print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}")
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print("-" * 60)
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ram = self.dump_ram()
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out = self.cpu.last_out
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self.cpu.last_out = None
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return {
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"pc": pc_before,
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"instr": instr,
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"cycles_added": cycles_added,
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"regs": c.regs.copy(),
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"lt": c.lt,
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"eq": c.eq,
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"sp": c.sp,
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"ram": ram,
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"out": out
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}
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# ----------------- boucle principale -----------------
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def run(self, max_steps: int = 100000):
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steps = 0
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while self.cpu.running and steps < max_steps:
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result = self.step()
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yield result
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steps += 1
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def dump_ram(self):
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print("\n========= RAM DUMP ========")
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for addr in range(0, 256, 8):
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chunk = self.ram[addr:addr+8]
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hex_values = " ".join(f"{b:02X}" for b in chunk)
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print(f"{addr:02X}: {hex_values}")
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return self.ram
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print("===========================\n")
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# ---------------------------------------------------------
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# LECTURE D'UN FICHIER .bin ET LANCEMENT
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# ---------------------------------------------------------
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if __name__ == "__main__":
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# Nom du fichier binaire à exécuter
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path =""
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args= sys.argv
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if (len(args) > 1):
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filename = args[1]
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print("filename: " + filename)
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with open(filename, "rb") as f:
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program = f.read()
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sim = Simulator(program)
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sim.run()
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else:
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print("Needs *.bin as parameter")
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