Tom/24H_du_code_2026
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compare: Tom:d85f8af7450efb8437376a2b11f3b97f1a039724
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No commits in common. "667fd60bda7b44392aea21ec7113b85a6e1be895" and "d85f8af7450efb8437376a2b11f3b97f1a039724" have entirely different histories.
667fd60bda ... d85f8af745

7 changed files with 37 additions and 239 deletions
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5
Epreuve3.py
View File

@ -11,7 +11,7 @@
# - Pile descendante, SP=255 # - Pile descendante, SP=255
# --------------------------------------------------------- # ---------------------------------------------------------
from dataclasses import dataclass, field from dataclasses import dataclass, field
import sys, time import sys
@dataclass @dataclass
@ -246,9 +246,8 @@ class Simulator:
steps = 0 steps = 0
while self.cpu.running and steps < max_steps: while self.cpu.running and steps < max_steps:
result = self.step() result = self.step()
# yield result yield result
steps += 1 steps += 1
time.sleep(0.05)
def dump_ram(self): def dump_ram(self):
print("\n========= RAM DUMP ========") print("\n========= RAM DUMP ========")

50
Fibbo16b.asm
View File

@ -1,50 +0,0 @@
_main:
MOV R0 1 ; b
SUB R1 R1 ; b
SUB R2 R2 ; a
SUB R3 R3 ; a
_loop:
OUT R2
OUT R3
PUSH R0 ; Sauvegarde de b
PUSH R1
; R0 R1 => b R2 R3 => a. Retourne b = b + a = c
PUSH R1
SUB R1 R1
SUB R1 R2
SUB R0 R1
POP R1 ; R0 = R0 + R2
CMP R0 R2 ; Si overflow, il faut +1 R3 (a oct fort)
JLT _add16cr1debut
JMP _add16cr1fin
_add16cr1debut:
SUB R3 255
_add16cr1fin:
PUSH R0
SUB R0 R0
SUB R0 R3
SUB R1 R0
POP R0 ; R1 = R1 + R3
CMP R1 R3
JLT _add16cr2debut
JMP _add16cr2fin
_add16cr2debut:
JMP _end
_add16cr2fin:
POP R3 ; Reprise de b
POP R2
JMP _loop
_end:
POP R3
POP R2
RET

37
Interpreteur.py
View File

@ -12,6 +12,7 @@
# --------------------------------------------------------- # ---------------------------------------------------------
import sys, time import sys, time
import uasyncio as asyncio import uasyncio as asyncio
@ -131,8 +132,8 @@ class Simulator:
r = b & 0b11 r = b & 0b11
instr = f"POP R{r}" instr = f"POP R{r}"
c.regs[r] = self.pop() c.regs[r] = self.pop()
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(r, c.regs[r]) setRegisterCallback(r, c.regs[r])
# --- MOV Rx valeur / SUB Rx valeur / CMP Rx valeur --- # --- MOV Rx valeur / SUB Rx valeur / CMP Rx valeur ---
elif (b & 0b11111100) == 0b11100000: # MOV Rx valeur elif (b & 0b11111100) == 0b11100000: # MOV Rx valeur
@ -141,8 +142,8 @@ class Simulator:
size = 2 size = 2
instr = f"MOV R{r}, {imm}" instr = f"MOV R{r}, {imm}"
c.regs[r] = imm c.regs[r] = imm
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(r, c.regs[r]) setRegisterCallback(r, c.regs[r])
elif (b & 0b11111100) == 0b00010000: # SUB Rx valeur elif (b & 0b11111100) == 0b00010000: # SUB Rx valeur
r = b & 0b11 r = b & 0b11
@ -150,8 +151,8 @@ class Simulator:
size = 2 size = 2
instr = f"SUB R{r}, {imm}" instr = f"SUB R{r}, {imm}"
c.regs[r] = (c.regs[r] - imm) & 0xFF c.regs[r] = (c.regs[r] - imm) & 0xFF
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(r, c.regs[r]) setRegisterCallback(r, c.regs[r])
elif (b & 0b11111100) == 0b10010000: # CMP Rx valeur elif (b & 0b11111100) == 0b10010000: # CMP Rx valeur
r = b & 0b11 r = b & 0b11
@ -168,16 +169,16 @@ class Simulator:
src = b & 0b11 src = b & 0b11
instr = f"MOV R{dst}, R{src}" instr = f"MOV R{dst}, R{src}"
c.regs[dst] = c.regs[src] c.regs[dst] = c.regs[src]
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(dst, c.regs[dst]) setRegisterCallback(dst, c.regs[dst])
elif (b & 0b11110000) == 0b11010000: # SUB Rx Ry elif (b & 0b11110000) == 0b11010000: # SUB Rx Ry
dst = (b >> 2) & 0b11 dst = (b >> 2) & 0b11
src = b & 0b11 src = b & 0b11
instr = f"SUB R{dst}, R{src}" instr = f"SUB R{dst}, R{src}"
c.regs[dst] = (c.regs[dst] - c.regs[src]) & 0xFF c.regs[dst] = (c.regs[dst] - c.regs[src]) & 0xFF
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(dst, c.regs[dst]) setRegisterCallback(dst, c.regs[dst])
elif (b & 0b11110000) == 0b00110000: # CMP Rx Ry elif (b & 0b11110000) == 0b00110000: # CMP Rx Ry
dst = (b >> 2) & 0b11 dst = (b >> 2) & 0b11
@ -198,8 +199,8 @@ class Simulator:
eff = (addr + c.regs[src]) & 0xFF eff = (addr + c.regs[src]) & 0xFF
c.regs[dst] = self.ram[eff] c.regs[dst] = self.ram[eff]
extra_cycles = 1 # 2 octets -> 2 cycles +1 = 3 extra_cycles = 1 # 2 octets -> 2 cycles +1 = 3
if (self.registerCallback != None): if (setRegisterCallback != None):
self.registerCallback(dst, c.regs[dst]) setRegisterCallback(dst, c.regs[dst])
elif (b & 0b11110000) == 0b01110000: # STR Rx Ry _label elif (b & 0b11110000) == 0b01110000: # STR Rx Ry _label
dst = (b >> 2) & 0b11 dst = (b >> 2) & 0b11
@ -232,9 +233,9 @@ class Simulator:
mult = 1 if m == 0 else 100 mult = 1 if m == 0 else 100
pause_ms = mult * (v + 1) pause_ms = mult * (v + 1)
c.cycles += pause_ms # modélisation de la pause c.cycles += pause_ms # modélisation de la pause
# print(f"Sleep {pause_ms}ms...") print(f"Sleep {pause_ms}ms...")
time.sleep(pause_ms/1000) time.sleep(pause_ms/1000)
# print("BIPBIP") print("BIPBIP")
# if pc_before >= self.program_size: # if pc_before >= self.program_size:
# if 32 <= b <= 126: # if 32 <= b <= 126:
@ -262,9 +263,9 @@ class Simulator:
def report(self, pc_before: int, instr: str, cycles_added: int): def report(self, pc_before: int, instr: str, cycles_added: int):
c = self.cpu c = self.cpu
regs_str = " ".join(f"R{i}={c.regs[i]:02X}" for i in range(4)) regs_str = " ".join(f"R{i}={c.regs[i]:02X}" for i in range(4))
# print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}") print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}")
# print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}") print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}")
# print("-" * 60) print("-" * 60)
# ----------------- boucle principale ----------------- # ----------------- boucle principale -----------------
@ -277,7 +278,7 @@ class Simulator:
def StartCPU(program, callback, registerCallback): def StartCPU(program, callback, registerCallback):
sim = Simulator(program) sim = Simulator(program)
sim.setMotorCallback(callback) sim.setMotorCallback(callback)
sim.setRegisterCallback(registerCallback) sim.setRegisterCallback(setRegisterCallback)
while sim.cpu.running: while sim.cpu.running:
sim.run(max_steps = 1) sim.run(max_steps = 1)
#time.sleep(0.1) #time.sleep(0.1)

32
LED.asm
View File

@ -1,32 +0,0 @@
_main:
SUB R0 R0
SUB R1 R1
SUB R2 R2
SUB R3 R3
_loop1:
SUB R0 245
TIM 1
CMP R0 220
JLT _loop1
_loop2:
SUB R1 245
TIM 1
CMP R1 220
JLT _loop2
_loop3:
SUB R2 245
TIM 1
CMP R2 220
JLT _loop3
_loop4:
SUB R3 245
TIM 1
CMP R3 220
JLT _loop4
RET

127
main.py
View File

@ -21,97 +21,6 @@ oled = SSD1306_I2C(128, 64, alphabot.i2c)
oled.fill(0) oled.fill(0)
oled.show() oled.show()
bitmapSII = bytes([
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc0,
0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xf0, 0xf0, 0xf0, 0xf8, 0xf8, 0xf8, 0xf8, 0x7c, 0xfc, 0xfc, 0xfc,
0xfc, 0xfc, 0xfc, 0x7c, 0x7e, 0x7e, 0x7e, 0x7c, 0x7c, 0x7c, 0x7c, 0xfc, 0xfc, 0xf8, 0xf8, 0xf0,
0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xc0, 0xe0, 0xe0,
0xe0, 0xc0, 0x80, 0x20, 0x10, 0x10, 0x18, 0x08, 0x0c, 0x0e, 0x06, 0x07, 0x7f, 0x7f, 0x3f, 0x3f,
0x1f, 0x0f, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x7f, 0x3f,
0x3f, 0x1f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x01, 0x01, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x80, 0xc0, 0xf0, 0xf8, 0xfc, 0xfe, 0xfe, 0xff, 0x7f, 0x3f, 0x0f, 0x07, 0x07,
0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf0, 0xf8, 0xf8, 0xfc,
0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf8, 0xf8,
0xfc, 0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xc0, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc,
0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xf8, 0xfc, 0xfc, 0xfc, 0xc0, 0xc0, 0xc0,
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x03, 0x0f, 0x1f, 0x3f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfc,
0xf8, 0xe0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x3f, 0x3f, 0x3f, 0x1f,
0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x1f, 0x3f, 0x3f, 0x3f, 0x03, 0x03, 0x03,
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x0f, 0x7f, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xfc, 0xff, 0xff, 0xff, 0xff,
0xff, 0x7f, 0x1f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x07, 0x07,
0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x20, 0x30, 0x3c, 0x3e, 0x3f, 0x3f, 0x1f, 0x0f, 0x07, 0x07, 0x03, 0x01,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x01,
0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
oled.write_data(bitmapSII)
class FoursNeoPixel():
def __init__(self, pin_number):
self._pin = pin_number
self._max_leds = 4
self._leds = neopixel.NeoPixel(self._pin, 4)
def set_led(self, addr, red, green, blue):
if addr >= 0 and addr < self._max_leds:
# coded on BGR
self._leds[addr] = (blue, green, red)
def set_led2(self, addr, rgb):
if addr >= 0 and addr < self._max_leds:
# coded on BGR
self._leds[addr] = rgb
def show(self):
self._leds.write()
def clear(self):
for i in range (0, self._max_leds):
self.set_led(i, 0,0,0)
self.show()
leds = FoursNeoPixel(alphabot.pin_RGB)
def motorCallback(motG, motD): def motorCallback(motG, motD):
@ -119,22 +28,14 @@ def motorCallback(motG, motD):
sMotD = 1 - ((motD >> 2) & 0b10) sMotD = 1 - ((motD >> 2) & 0b10)
motG = ((motG & 0b0111) * sMotG) * motorSpeedFactor / 7 motG = ((motG & 0b0111) * sMotG) * motorSpeedFactor / 7
motD = (((motD & 0b0111) * sMotD) * motorSpeedFactor / 7) * motorDCompensation motD = (((motD & 0b0111) * sMotD) * motorSpeedFactor / 7) * motorDCompensation
# print("Mot G :", motG) print("Mot G :", motG)
# print("Mot D :", motD) print("Mot D :", motD)
alphabot.setMotors(left=motG, right=motD) alphabot.setMotors(left=motG, right=motD)
def registerCallback(register, value): def registerCallback(register, value):
global leds print(f"Register R{register} changed to {value}")
# print(f"Register R{register} changed to {value}") pass
if (register == 0):
leds.set_led(0, value, abs(127 - value), 255 - value)
elif (register == 1):
leds.set_led(1, value, abs(127 - value), 255 - value)
elif (register == 2):
leds.set_led(2, value, abs(127 - value), 255 - value)
else:
leds.set_led(3, value, abs(127 - value), 255 - value)
leds.show()
# to know COM port used when connected on PC: # to know COM port used when connected on PC:
@ -147,29 +48,13 @@ robotName = 'Nogard'
toSend = [] toSend = []
def onMsgToRobot(data:str|bytes): def onMsgToRobot(data:str|bytes):
global useLED, useMotor
if (not ("useLED" in globals())):
useLED = False
if (not ("useMotor" in globals())):
useMotor = True
"""Function to call when a message sent by PC is received """Function to call when a message sent by PC is received
:param data: message received""" :param data: message received"""
checksum = binascii.crc32(data) checksum = binascii.crc32(data)
print('received', data, '=>', checksum) print('received', data, '=>', checksum)
print(data) print(data)
if (data[0] == "#"): StartCPU(data, motorCallback, registerCallback)
data = data[1:]
if (data == "LED ON"):
useLED = True
elif (data == "LED OFF"):
useLED = False
elif (data == "MOTOR ON"):
useMotor = True
elif (data == "MOTOR OFF"):
useMotor = False
else:
StartCPU(data, motorCallback if useMotor else None, registerCallback if useLED else None)
alphabot.stop() alphabot.stop()

23
notes.txt
View File

@ -153,24 +153,19 @@ TIM valeur ;génération binaire 11111000 mvvvvvvv
1000ms = 85cm (vitesse 3)
toupie 76 100ms = 360 + 90°
42
76
Connexion
{"type": "connect", "name": "Nogard"} {"type": "connect", "name": "Nogard"}
Commandes annexes {"type": "msg", "format": "base64", "string": "4Dvw+IKA"}
{"type": "msg", "format": "str", "string": "#LED ON"}
{"type": "msg", "format": "str", "string": "#LED OFF"}
{"type": "msg", "format": "str", "string": "#MOTOR ON"}
{"type": "msg", "format": "str", "string": "#MOTOR OFF"}
Fibbo 8bits Demi tour
{"type": "msg", "format": "base64", "string": "4ADhAfDx4gBc2d5RVzTAEkAF4EGA"} {"type": "msg", "format": "base64", "string": "4Dvw+IHgAPCA"}
Fibbo 16bits
{"type": "msg", "format": "base64", "string": "4AHV2t/y8/LzoKGh1dbRYTLAFUAXE/+g0NPUYDfAIUAjQCdjYkAHY2KA"}
LED
{"type": "msg", "format": "base64", "string": "0NXa3xD1+AGQ3MAEEfX4AZHcwAwS9fgBktzAFBP1+AGT3MAcgA=="}
Demi tour + fuite Demi tour + fuite
{"type": "msg", "format": "base64", "string": "4Dvw+ID4MuAA8Phk4Mzw+KXgAPDgAPD4ZIA="} {"type": "msg", "format": "base64", "string": "4Dvw+ID4MuAA8Phk4Mzw+KXgAPDgAPD4ZIA="}

BIN
out.bin
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