Gestion DT

2026-03-21 20:54:39 +01:00
parent eb834b8f72
commit f28819d288
19 changed files with 16 additions and 22 deletions
@@ -70,12 +70,10 @@ class Simulator:
        extra_cycles = 0  # pour LDR/STR/TIM

        # --- instructions 2 octets à opcode fixe ---
-        #print(pc_before)
-        #print(self.program_size)
-        if c.after_ret:
-            instr = f"DB 0x{b:02X}"
+        #if c.after_ret:
+        #    instr = f"DB 0x{b:02X}"

-        elif b == 0x00:  # CALL _label
+        if b == 0x00:  # CALL _label
            addr = self.fetch_byte()
            size = 2
            instr = f"CALL {addr}"
@@ -206,14 +204,10 @@ class Simulator:
            pause_ms = mult * (v + 1)
            c.cycles += pause_ms  # modélisation de la pause

-       # if pc_before >= self.program_size:
-       #     if 32 <= b <= 126:
-       #         instr = f"DB 0x{b:02X} ('{chr(b)}')"
-       #     else:
-       #         instr = f"DB 0x{b:02X}"
        else:
-            instr = f"UNKNOWN 0x{b:02X}"
-            c.running = False
+            instr = f"DB 0x{b:02X}"
+        #    instr = f"UNKNOWN 0x{b:02X}"
+        #    c.running = False



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