Epreuve2 Version 2 (Gestion des DB)
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BalkisJerad
parent
f28819d288
commit
ea5f707d05
@ -4,10 +4,14 @@ _main:
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MOV R1 1 ; b
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OUT R0 ; print 0
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_data1:
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DB 0 ;00000000
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DB 'C' ;01000011
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_loop:
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OUT R1 ; print b
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MOV R2 0 ; 0
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MOV R3 R0 ; c = a
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MOV R3 R0 ; c = a
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SUB R2 R1 ; 0 - b
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SUB R3 R2 ; a - (0 - b) = a - -b = a + b
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@ -19,4 +23,5 @@ _loop:
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JMP _loop
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_end:
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LDR R2 R3 _data1
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RET
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178
Epreuve2.py
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178
Epreuve2.py
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@ -0,0 +1,178 @@
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import sys
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# --- Configuration des instructions (Inchangée) ---
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instructions = {
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"DB": {"ins": "DB", "args": [{"isRegister": False, "isValue": True, "isLabel": False}]},
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"CALL": {"ins": "CALL", "args": [{"isRegister": False, "isValue": False, "isLabel": True}]},
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"RET": {"ins": "RET", "args": []},
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"JMP": {"ins": "JMP", "args": [{"isRegister": False, "isValue": False, "isLabel": True}]},
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"JLT": {"ins": "JLT", "args": [{"isRegister": False, "isValue": False, "isLabel": True}]},
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"JEQ": {"ins": "JEQ", "args": [{"isRegister": False, "isValue": False, "isLabel": True}]},
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"PUSH": {"ins": "PUSH", "args": [{"isRegister": True, "isValue": False, "isLabel": False}]},
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"POP": {"ins": "POP", "args": [{"isRegister": True, "isValue": False, "isLabel": False}]},
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"MOV": {"ins": "MOV", "args": [{"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": True, "isValue": True, "isLabel": False}]},
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"SUB": {"ins": "SUB", "args": [{"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": True, "isValue": True, "isLabel": False}]},
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"CMP": {"ins": "CMP", "args": [{"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": True, "isValue": True, "isLabel": False}]},
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"LDR": {"ins": "LDR", "args": [{"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": False, "isValue": False, "isLabel": True}]},
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"STR": {"ins": "STR", "args": [{"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": True, "isValue": False, "isLabel": False}, {"isRegister": False, "isValue": False, "isLabel": True}]},
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"OUT": {"ins": "OUT", "args": [{"isRegister": True, "isValue": False, "isLabel": False}]},
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"TIM": {"ins": "TIM", "args": [{"isRegister": False, "isValue": True, "isLabel": False}]}
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}
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# --- Fonctions Utilitaires (Inchangées) ---
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def valueToInt(arg):
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try: return int(arg)
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except: return ord(arg[1])
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def registerToDec(reg): return int(reg[1])
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def testArgIsRegister(arg):
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if len(arg) != 2 or arg[0] != "R": return False
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try: return 0 <= int(arg[1]) <= 3
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except: return False
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def testArgIsValue(arg):
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try:
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if 0 <= int(arg) <= 255: return True
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except: pass
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if len(arg) == 3 and arg[0] == arg[2] == "'": return True
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return False
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def testArgIsLabel(arg, twoDotsIncluded=False):
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if not arg or arg[0] != "_": return False
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body = arg[1:-1] if twoDotsIncluded else arg[1:]
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if twoDotsIncluded and arg[-1] != ":": return False
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return all(c in "abcdefghijklmnopqrstuvwxyz0123456789_" for c in body)
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# --- Fonctions de Conversion (Inchangées) ---
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def convertInsDB(args): return {"opcode": [valueToInt(args[0])], "is_db": True}
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def convertInsCALL(args): return {"opcode": [0x00, "label"], "label": args[0]}
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def convertInsRET(args): return {"opcode": [0x80]}
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def convertInsJMP(args): return {"opcode": [0x40, "label"], "label": args[0]}
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def convertInsJLT(args): return {"opcode": [0xC0, "label"], "label": args[0]}
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def convertInsJEQ(args): return {"opcode": [0x20, "label"], "label": args[0]}
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def convertInsPUSH(args): return {"opcode": [0xA0 | registerToDec(args[0])]}
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def convertInsPOP(args): return {"opcode": [0x60 | registerToDec(args[0])]}
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def convertInsMOV(args):
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idReg0 = registerToDec(args[0])
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if testArgIsRegister(args[1]): return {"opcode": [0x50 | (idReg0 << 2) | registerToDec(args[1])]}
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return {"opcode": [0xE0 | idReg0, valueToInt(args[1])]}
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def convertInsSUB(args):
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idReg0 = registerToDec(args[0])
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if testArgIsRegister(args[1]): return {"opcode": [0xD0 | (idReg0 << 2) | registerToDec(args[1])]}
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return {"opcode": [0x10 | idReg0, valueToInt(args[1])]}
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def convertInsCMP(args):
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idReg0 = registerToDec(args[0])
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if testArgIsRegister(args[1]): return {"opcode": [0x30 | (idReg0 << 2) | registerToDec(args[1])]}
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return {"opcode": [0x90 | idReg0, valueToInt(args[1])]}
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def convertInsLDR(args):
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return {"opcode": [0xB0 | (registerToDec(args[0]) << 2) | registerToDec(args[1]), "label"], "label": args[2]}
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def convertInsSTR(args):
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return {"opcode": [0x70 | (registerToDec(args[0]) << 2) | registerToDec(args[1]), "label"], "label": args[2]}
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def convertInsOUT(args): return {"opcode": [0xF0 | registerToDec(args[0])]}
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def convertInsTIM(args): return {"opcode": [0xF8, valueToInt(args[0])]}
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# --- Assembleur ---
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def assemble(path):
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labels = {}
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code_elements = []
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data_elements = []
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with open(path, "r") as f:
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lines = f.readlines()
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current_pending_labels = []
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for line_num, line in enumerate(lines, 1):
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line = line.split(";")[0].strip()
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if not line: continue
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parts = line.split()
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# Traitement des labels (on peut en avoir plusieurs de suite)
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while parts and testArgIsLabel(parts[0], True):
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label_name = parts[0][:-1]
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current_pending_labels.append(label_name)
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parts = parts[1:] # On retire le label et on continue sur la même ligne
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if not parts: continue # Ligne ne contenait que des labels
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instr_name = parts[0]
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args = parts[1:]
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try:
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res = globals()[f"convertIns{instr_name}"](args)
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res["attached_labels"] = current_pending_labels
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current_pending_labels = []
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if res.get("is_db"):
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data_elements.append(res)
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else:
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code_elements.append(res)
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except Exception as e:
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print(f"ERROR Line {line_num}: {instr_name} -> {e}")
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sys.exit(1)
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# Si des labels traînent à la toute fin du fichier
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if current_pending_labels:
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# On les attache à un élément factice à la fin de la data
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data_elements.append({"opcode": [], "attached_labels": current_pending_labels, "is_db": True})
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# CALCUL DES ADRESSES FINALES
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final_labels = {}
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current_pc = 0
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# 1. On passe sur le CODE d'abord
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for item in code_elements:
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for lbl in item["attached_labels"]:
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final_labels[lbl] = current_pc
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current_pc += len(item["opcode"])
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# 2. On passe sur la DATA ensuite
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for item in data_elements:
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for lbl in item["attached_labels"]:
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final_labels[lbl] = current_pc
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current_pc += len(item["opcode"])
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# GÉNÉRATION DU BYTECODE
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final_bytecode = []
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# Ordre : Code puis Data
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for item in code_elements + data_elements:
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for op in item["opcode"]:
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if op == "label":
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label_target = item["label"]
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if label_target not in final_labels:
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print(f"ERROR: Label '{label_target}' missing!")
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sys.exit(1)
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final_bytecode.append(final_labels[label_target])
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else:
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final_bytecode.append(op)
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return final_bytecode, final_labels
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if __name__ == "__main__":
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if len(sys.argv) < 2:
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print("Usage: python asm.py <file.asm>")
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sys.exit(1)
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path = sys.argv[1]
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bytecode, labels_map = assemble(path)
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# Affichage propre
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print("\n" + "="*50)
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print(f" ASSEMBLY PREVIEW: {path}")
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print("="*50)
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print(f"{'ADDR':<7} | {'HEX':<5} | {'BINARY':<10}")
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print("-" * 30)
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for i, b in enumerate(bytecode):
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# On cherche si un label pointe ici pour l'afficher
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lbl_str = ""
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for name, addr in labels_map.items():
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if addr == i: lbl_str += f" ({name})"
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print(f"0x{i:02X} | {b:02x} | {b:08b} {lbl_str}")
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print("="*50 + "\n")
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with open(path + ".bin", "wb") as file:
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file.write(bytes(bytecode))
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print(f"Success: {path}.bin generated.")
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@ -69,10 +69,6 @@ class Simulator:
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size = 1 # taille en octets (1 ou 2)
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extra_cycles = 0 # pour LDR/STR/TIM
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# --- instructions 2 octets à opcode fixe ---
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#if c.after_ret:
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# instr = f"DB 0x{b:02X}"
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if b == 0x00: # CALL _label
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addr = self.fetch_byte()
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size = 2
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@ -204,8 +200,9 @@ class Simulator:
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pause_ms = mult * (v + 1)
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c.cycles += pause_ms # modélisation de la pause
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else:
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else: # Si DB est apres RET on n atteind pas ce bloc
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instr = f"DB 0x{b:02X}"
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size = 0 # DB n'est pas une INS
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# instr = f"UNKNOWN 0x{b:02X}"
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# c.running = False
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