diff --git a/assembleur.py b/assembleur.py
new file mode 100644
index 0000000..7c3b901
--- /dev/null
+++ b/assembleur.py
@@ -0,0 +1,142 @@
+
+instructions = {
+    "DB" : {
+        "args": [{
+            "isRegister": False,
+            "isValue": True,
+            "isLabel": False
+        }]
+    },
+    "CALL": {
+        "args": [{
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "RET": {
+        "args": []
+    },
+    "JMP": {
+        "args": [{
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "JLT": {
+        "args": [{
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "JEQ": {
+        "args": [{
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "PUSH": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        }]
+    },
+    "POP": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        }]
+    },
+    "MOV": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": True,
+            "isValue": True,
+            "isLabel": False
+        }]
+    },
+    "SUB": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": True,
+            "isValue": True,
+            "isLabel": False
+        }]
+    },
+    "CMP": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": True,
+            "isValue": True,
+            "isLabel": False
+        }]
+    },
+    "LDR": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "STR": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        },
+        {
+            "isRegister": False,
+            "isValue": False,
+            "isLabel": True
+        }]
+    },
+    "OUT": {
+        "args": [{
+            "isRegister": True,
+            "isValue": False,
+            "isLabel": False
+        }]
+    },
+    "TIM": {
+        "args": [{
+            "isRegister": False,
+            "isValue": True,
+            "isLabel": False
+        }]
+    }
+}
+
+
+print(instructions)
\ No newline at end of file
diff --git a/notes.txt b/notes.txt
index fed892a..17d93d8 100644
--- a/notes.txt
+++ b/notes.txt
@@ -1,7 +1,7 @@
 
 a = 0
 b = 1
-c = 1
+c = ?
 
 print a