diff --git a/Fibbo16b.asm b/Fibbo16b.asm new file mode 100644 index 0000000..3895d44 --- /dev/null +++ b/Fibbo16b.asm @@ -0,0 +1,46 @@ +_main: + MOV R0 1 ; b + SUB R1 R1 ; b + SUB R2 R2 ; a + SUB R3 R3 ; a + +_loop: + OUT R2 + OUT R3 + + PUSH R0 ; Sauvegarde de b + PUSH R1 + + PUSH R1 ; R0 R1 => b R2 R3 => a. Retourne b = b + a = c + SUB R1 R1 + SUB R1 R2 + SUB R0 R1 + POP R1 ; R0 = R0 + R2 + + CMP R0 R2 ; Si overflow, il faut +1 R3 (a oct fort) + JLT _add16cr1debut + JMP _add16cr1fin +_add16cr1debut: + SUB R3 255 +_add16cr1fin: + + PUSH R0 + SUB R0 R0 + SUB R0 R3 + SUB R1 R0 + POP R0 ; R1 = R1 + R3 + CMP R1 R3 + JLT _add16cr2debut + JMP _add16cr2fin +_add16cr2debut: + JMP _end +_add16cr2fin: + + POP R3 ; Reprise de b + POP R2 + JMP _loop + +_end: + POP R3 + POP R2 + RET diff --git a/Fibbonacci 16Bits.png b/Fibbonacci 16Bits.png new file mode 100644 index 0000000..df4e9ff Binary files /dev/null and b/Fibbonacci 16Bits.png differ diff --git a/Interpreteur.py b/Interpreteur.py index 2e79e0b..bcaedd6 100644 --- a/Interpreteur.py +++ b/Interpreteur.py @@ -12,7 +12,6 @@ # --------------------------------------------------------- import sys, time - import uasyncio as asyncio @@ -132,8 +131,8 @@ class Simulator: r = b & 0b11 instr = f"POP R{r}" c.regs[r] = self.pop() - if (setRegisterCallback != None): - setRegisterCallback(r, c.regs[r]) + if (self.registerCallback != None): + self.registerCallback(r, c.regs[r]) # --- MOV Rx valeur / SUB Rx valeur / CMP Rx valeur --- elif (b & 0b11111100) == 0b11100000: # MOV Rx valeur @@ -142,8 +141,8 @@ class Simulator: size = 2 instr = f"MOV R{r}, {imm}" c.regs[r] = imm - if (setRegisterCallback != None): - setRegisterCallback(r, c.regs[r]) + if (self.registerCallback != None): + self.registerCallback(r, c.regs[r]) elif (b & 0b11111100) == 0b00010000: # SUB Rx valeur r = b & 0b11 @@ -151,8 +150,8 @@ class Simulator: size = 2 instr = f"SUB R{r}, {imm}" c.regs[r] = (c.regs[r] - imm) & 0xFF - if (setRegisterCallback != None): - setRegisterCallback(r, c.regs[r]) + if (self.registerCallback != None): + self.registerCallback(r, c.regs[r]) elif (b & 0b11111100) == 0b10010000: # CMP Rx valeur r = b & 0b11 @@ -169,16 +168,16 @@ class Simulator: src = b & 0b11 instr = f"MOV R{dst}, R{src}" c.regs[dst] = c.regs[src] - if (setRegisterCallback != None): - setRegisterCallback(dst, c.regs[dst]) + if (self.registerCallback != None): + self.registerCallback(dst, c.regs[dst]) elif (b & 0b11110000) == 0b11010000: # SUB Rx Ry dst = (b >> 2) & 0b11 src = b & 0b11 instr = f"SUB R{dst}, R{src}" c.regs[dst] = (c.regs[dst] - c.regs[src]) & 0xFF - if (setRegisterCallback != None): - setRegisterCallback(dst, c.regs[dst]) + if (self.registerCallback != None): + self.registerCallback(dst, c.regs[dst]) elif (b & 0b11110000) == 0b00110000: # CMP Rx Ry dst = (b >> 2) & 0b11 @@ -199,8 +198,8 @@ class Simulator: eff = (addr + c.regs[src]) & 0xFF c.regs[dst] = self.ram[eff] extra_cycles = 1 # 2 octets -> 2 cycles +1 = 3 - if (setRegisterCallback != None): - setRegisterCallback(dst, c.regs[dst]) + if (self.registerCallback != None): + self.registerCallback(dst, c.regs[dst]) elif (b & 0b11110000) == 0b01110000: # STR Rx Ry _label dst = (b >> 2) & 0b11 @@ -233,9 +232,9 @@ class Simulator: mult = 1 if m == 0 else 100 pause_ms = mult * (v + 1) c.cycles += pause_ms # modélisation de la pause - print(f"Sleep {pause_ms}ms...") + # print(f"Sleep {pause_ms}ms...") time.sleep(pause_ms/1000) - print("BIPBIP") + # print("BIPBIP") # if pc_before >= self.program_size: # if 32 <= b <= 126: @@ -263,9 +262,9 @@ class Simulator: def report(self, pc_before: int, instr: str, cycles_added: int): c = self.cpu regs_str = " ".join(f"R{i}={c.regs[i]:02X}" for i in range(4)) - print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}") - print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}") - print("-" * 60) + # print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}") + # print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}") + # print("-" * 60) # ----------------- boucle principale ----------------- @@ -278,7 +277,7 @@ class Simulator: def StartCPU(program, callback, registerCallback): sim = Simulator(program) sim.setMotorCallback(callback) - sim.setRegisterCallback(setRegisterCallback) + sim.setRegisterCallback(registerCallback) while sim.cpu.running: sim.run(max_steps = 1) #time.sleep(0.1) diff --git a/LED.asm b/LED.asm index e69de29..84d3425 100644 --- a/LED.asm +++ b/LED.asm @@ -0,0 +1,32 @@ +_main: + + SUB R0 R0 + SUB R1 R1 + SUB R2 R2 + SUB R3 R3 + +_loop1: + SUB R0 245 + TIM 1 + CMP R0 220 + JLT _loop1 + +_loop2: + SUB R1 245 + TIM 1 + CMP R1 220 + JLT _loop2 + +_loop3: + SUB R2 245 + TIM 1 + CMP R2 220 + JLT _loop3 + +_loop4: + SUB R3 245 + TIM 1 + CMP R3 220 + JLT _loop4 + + RET \ No newline at end of file diff --git a/Path.asm b/Path.asm index 1e32447..1f3be12 100644 --- a/Path.asm +++ b/Path.asm @@ -12,7 +12,7 @@ _main: MOV R0 51 OUT R0 - TIM 162 ; Ligne droite OK + TIM 165 ; Ligne droite OK MOV R0 49 ; 0b 0011 0001 OUT R0 diff --git a/main.py b/main.py index 730828d..3015e8b 100644 --- a/main.py +++ b/main.py @@ -21,6 +21,97 @@ oled = SSD1306_I2C(128, 64, alphabot.i2c) oled.fill(0) oled.show() +bitmapSII = bytes([ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc0, +0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xf0, 0xf0, 0xf0, 0xf8, 0xf8, 0xf8, 0xf8, 0x7c, 0xfc, 0xfc, 0xfc, +0xfc, 0xfc, 0xfc, 0x7c, 0x7e, 0x7e, 0x7e, 0x7c, 0x7c, 0x7c, 0x7c, 0xfc, 0xfc, 0xf8, 0xf8, 0xf0, +0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xc0, 0xe0, 0xe0, +0xe0, 0xc0, 0x80, 0x20, 0x10, 0x10, 0x18, 0x08, 0x0c, 0x0e, 0x06, 0x07, 0x7f, 0x7f, 0x3f, 0x3f, +0x1f, 0x0f, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x7f, 0x3f, +0x3f, 0x1f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x01, 0x01, 0x01, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x80, 0xc0, 0xf0, 0xf8, 0xfc, 0xfe, 0xfe, 0xff, 0x7f, 0x3f, 0x0f, 0x07, 0x07, +0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf0, 0xf8, 0xf8, 0xfc, +0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf8, 0xf8, +0xfc, 0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xc0, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, +0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xf8, 0xfc, 0xfc, 0xfc, 0xc0, 0xc0, 0xc0, +0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x03, 0x0f, 0x1f, 0x3f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfc, +0xf8, 0xe0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x3f, 0x3f, 0x3f, 0x1f, +0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x1f, 0x3f, 0x3f, 0x3f, 0x03, 0x03, 0x03, +0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x0f, 0x7f, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xfc, 0xff, 0xff, 0xff, 0xff, +0xff, 0x7f, 0x1f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x07, 0x07, +0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x20, 0x30, 0x3c, 0x3e, 0x3f, 0x3f, 0x1f, 0x0f, 0x07, 0x07, 0x03, 0x01, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x01, +0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]) +oled.write_data(bitmapSII) + + +class FoursNeoPixel(): + def __init__(self, pin_number): + self._pin = pin_number + self._max_leds = 4 + self._leds = neopixel.NeoPixel(self._pin, 4) + + def set_led(self, addr, red, green, blue): + if addr >= 0 and addr < self._max_leds: + # coded on BGR + self._leds[addr] = (blue, green, red) + + def set_led2(self, addr, rgb): + if addr >= 0 and addr < self._max_leds: + # coded on BGR + self._leds[addr] = rgb + def show(self): + self._leds.write() + def clear(self): + for i in range (0, self._max_leds): + self.set_led(i, 0,0,0) + self.show() +leds = FoursNeoPixel(alphabot.pin_RGB) + def motorCallback(motG, motD): @@ -28,14 +119,22 @@ def motorCallback(motG, motD): sMotD = 1 - ((motD >> 2) & 0b10) motG = ((motG & 0b0111) * sMotG) * motorSpeedFactor / 7 motD = (((motD & 0b0111) * sMotD) * motorSpeedFactor / 7) * motorDCompensation - print("Mot G :", motG) - print("Mot D :", motD) + # print("Mot G :", motG) + # print("Mot D :", motD) alphabot.setMotors(left=motG, right=motD) def registerCallback(register, value): - print(f"Register R{register} changed to {value}") - pass - + global leds + # print(f"Register R{register} changed to {value}") + if (register == 0): + leds.set_led(0, value, abs(127 - value), 255 - value) + elif (register == 1): + leds.set_led(1, value, abs(127 - value), 255 - value) + elif (register == 2): + leds.set_led(2, value, abs(127 - value), 255 - value) + else: + leds.set_led(3, value, abs(127 - value), 255 - value) + leds.show() # to know COM port used when connected on PC: @@ -48,14 +147,30 @@ robotName = 'Nogard' toSend = [] def onMsgToRobot(data:str|bytes): + global useLED, useMotor + if (not ("useLED" in globals())): + useLED = False + if (not ("useMotor" in globals())): + useMotor = True """Function to call when a message sent by PC is received :param data: message received""" checksum = binascii.crc32(data) print('received', data, '=>', checksum) print(data) - StartCPU(data, motorCallback, registerCallback) - alphabot.stop() + if (data[0] == "#"): + data = data[1:] + if (data == "LED ON"): + useLED = True + elif (data == "LED OFF"): + useLED = False + elif (data == "MOTOR ON"): + useMotor = True + elif (data == "MOTOR OFF"): + useMotor = False + else: + StartCPU(data, motorCallback if useMotor else None, registerCallback if useLED else None) + alphabot.stop() async def robotMainTask(bleConnection): diff --git a/notes.txt b/notes.txt index 95af3ae..e222239 100644 --- a/notes.txt +++ b/notes.txt @@ -153,24 +153,31 @@ TIM valeur ;génération binaire 11111000 mvvvvvvv -1000ms = 85cm (vitesse 3) -toupie 76 100ms = 360 + 90° - -42 -76 - +Connexion {"type": "connect", "name": "Nogard"} -{"type": "msg", "format": "base64", "string": "4Dvw+IKA"} +Commandes annexes +{"type": "msg", "format": "str", "string": "#LED ON"} +{"type": "msg", "format": "str", "string": "#LED OFF"} +{"type": "msg", "format": "str", "string": "#MOTOR ON"} +{"type": "msg", "format": "str", "string": "#MOTOR OFF"} -Demi tour -{"type": "msg", "format": "base64", "string": "4Dvw+IHgAPCA"} +Fibbo 8bits +{"type": "msg", "format": "base64", "string": "4ADhAfDx4gBc2d5RVzTAEkAF4EGA"} + +Fibbo 16bits +{"type": "msg", "format": "base64", "string": "4AHV2t/y8/LzoKGh1dbRYTLAFUAXE/+g0NPUYDfAIUAjQCdjYkAHY2KA"} + +LED +{"type": "msg", "format": "base64", "string": "0NXa3xD1+AGQ3MAEEfX4AZHcwAwS9fgBktzAFBP1+AGT3MAcgA=="} Demi tour + fuite {"type": "msg", "format": "base64", "string": "4Dvw+ID4MuAA8Phk4Mzw+KXgAPDgAPD4ZIA="} Parcours -{"type": "msg", "format": "base64", "string": "4BHw+ILgIvD4guAz8Pii4DHw+ILgM/D4mOAT8PiC4DPw+IjgAPCA4ADw+GSA"} +{"type": "msg", "format": "base64", "string": "4BHw+ILgIvD4guAz8Pil4DHw+ILgM/D4mOAT8PiC4DPw+IjgAPCA4ADw+GSA"} + + diff --git a/out.bin b/out.bin index 983ba41..9f6357d 100644 Binary files a/out.bin and b/out.bin differ