Fibbo16bits
This commit is contained in:
parent
789c2ad1b9
commit
7069455fa6
@ -11,7 +11,7 @@
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# - Pile descendante, SP=255
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# ---------------------------------------------------------
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from dataclasses import dataclass, field
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import sys
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import sys, time
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@dataclass
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@ -244,8 +244,9 @@ class Simulator:
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steps = 0
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while self.cpu.running and steps < max_steps:
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result = self.step()
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yield result
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# yield result
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steps += 1
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time.sleep(0.05)
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# ---------------------------------------------------------
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50
Fibbo16b.asm
Normal file
50
Fibbo16b.asm
Normal file
@ -0,0 +1,50 @@
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_main:
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MOV R0 1 ; b
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SUB R1 R1 ; b
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SUB R2 R2 ; a
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SUB R3 R3 ; a
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_loop:
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OUT R2
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OUT R3
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PUSH R0 ; Sauvegarde de b
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PUSH R1
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; R0 R1 => b R2 R3 => a. Retourne b = b + a = c
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PUSH R1
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SUB R1 R1
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SUB R1 R2
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SUB R0 R1
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POP R1 ; R0 = R0 + R2
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CMP R0 R2 ; Si overflow, il faut +1 R3 (a oct fort)
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JLT _add16cr1debut
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JMP _add16cr1fin
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_add16cr1debut:
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SUB R3 255
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_add16cr1fin:
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PUSH R0
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SUB R0 R0
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SUB R0 R3
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SUB R1 R0
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POP R0 ; R1 = R1 + R3
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CMP R1 R3
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JLT _add16cr2debut
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JMP _add16cr2fin
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_add16cr2debut:
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JMP _end
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_add16cr2fin:
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POP R3 ; Reprise de b
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POP R2
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JMP _loop
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_end:
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POP R3
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POP R2
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RET
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@ -12,7 +12,6 @@
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# ---------------------------------------------------------
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import sys, time
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import uasyncio as asyncio
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@ -132,8 +131,8 @@ class Simulator:
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r = b & 0b11
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instr = f"POP R{r}"
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c.regs[r] = self.pop()
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if (setRegisterCallback != None):
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setRegisterCallback(r, c.regs[r])
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if (self.registerCallback != None):
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self.registerCallback(r, c.regs[r])
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# --- MOV Rx valeur / SUB Rx valeur / CMP Rx valeur ---
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elif (b & 0b11111100) == 0b11100000: # MOV Rx valeur
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@ -142,8 +141,8 @@ class Simulator:
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size = 2
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instr = f"MOV R{r}, {imm}"
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c.regs[r] = imm
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if (setRegisterCallback != None):
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setRegisterCallback(r, c.regs[r])
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if (self.registerCallback != None):
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self.registerCallback(r, c.regs[r])
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elif (b & 0b11111100) == 0b00010000: # SUB Rx valeur
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r = b & 0b11
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@ -151,8 +150,8 @@ class Simulator:
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size = 2
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instr = f"SUB R{r}, {imm}"
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c.regs[r] = (c.regs[r] - imm) & 0xFF
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if (setRegisterCallback != None):
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setRegisterCallback(r, c.regs[r])
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if (self.registerCallback != None):
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self.registerCallback(r, c.regs[r])
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elif (b & 0b11111100) == 0b10010000: # CMP Rx valeur
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r = b & 0b11
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@ -169,16 +168,16 @@ class Simulator:
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src = b & 0b11
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instr = f"MOV R{dst}, R{src}"
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c.regs[dst] = c.regs[src]
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if (setRegisterCallback != None):
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setRegisterCallback(dst, c.regs[dst])
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if (self.registerCallback != None):
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self.registerCallback(dst, c.regs[dst])
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elif (b & 0b11110000) == 0b11010000: # SUB Rx Ry
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dst = (b >> 2) & 0b11
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src = b & 0b11
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instr = f"SUB R{dst}, R{src}"
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c.regs[dst] = (c.regs[dst] - c.regs[src]) & 0xFF
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if (setRegisterCallback != None):
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setRegisterCallback(dst, c.regs[dst])
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if (self.registerCallback != None):
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self.registerCallback(dst, c.regs[dst])
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elif (b & 0b11110000) == 0b00110000: # CMP Rx Ry
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dst = (b >> 2) & 0b11
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@ -199,8 +198,8 @@ class Simulator:
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eff = (addr + c.regs[src]) & 0xFF
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c.regs[dst] = self.ram[eff]
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extra_cycles = 1 # 2 octets -> 2 cycles +1 = 3
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if (setRegisterCallback != None):
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setRegisterCallback(dst, c.regs[dst])
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if (self.registerCallback != None):
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self.registerCallback(dst, c.regs[dst])
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elif (b & 0b11110000) == 0b01110000: # STR Rx Ry _label
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dst = (b >> 2) & 0b11
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@ -233,9 +232,9 @@ class Simulator:
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mult = 1 if m == 0 else 100
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pause_ms = mult * (v + 1)
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c.cycles += pause_ms # modélisation de la pause
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print(f"Sleep {pause_ms}ms...")
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# print(f"Sleep {pause_ms}ms...")
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time.sleep(pause_ms/1000)
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print("BIPBIP")
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# print("BIPBIP")
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# if pc_before >= self.program_size:
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# if 32 <= b <= 126:
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@ -263,9 +262,9 @@ class Simulator:
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def report(self, pc_before: int, instr: str, cycles_added: int):
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c = self.cpu
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regs_str = " ".join(f"R{i}={c.regs[i]:02X}" for i in range(4))
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print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}")
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print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}")
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print("-" * 60)
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# print(f"PC={pc_before:02X} {instr:20s} +Cycles={cycles_added:3d} Total={c.cycles}")
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# print(f" {regs_str} LT={c.lt} EQ={c.eq} SP={c.sp}")
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# print("-" * 60)
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# ----------------- boucle principale -----------------
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@ -278,7 +277,7 @@ class Simulator:
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def StartCPU(program, callback, registerCallback):
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sim = Simulator(program)
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sim.setMotorCallback(callback)
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sim.setRegisterCallback(setRegisterCallback)
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sim.setRegisterCallback(registerCallback)
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while sim.cpu.running:
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sim.run(max_steps = 1)
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#time.sleep(0.1)
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32
LED.asm
32
LED.asm
@ -0,0 +1,32 @@
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_main:
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SUB R0 R0
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SUB R1 R1
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SUB R2 R2
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SUB R3 R3
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_loop1:
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SUB R0 245
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TIM 1
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CMP R0 220
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JLT _loop1
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_loop2:
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SUB R1 245
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TIM 1
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CMP R1 220
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JLT _loop2
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_loop3:
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SUB R2 245
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TIM 1
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CMP R2 220
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JLT _loop3
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_loop4:
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SUB R3 245
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TIM 1
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CMP R3 220
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JLT _loop4
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RET
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129
main.py
129
main.py
@ -21,6 +21,97 @@ oled = SSD1306_I2C(128, 64, alphabot.i2c)
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oled.fill(0)
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oled.show()
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bitmapSII = bytes([
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xc0,
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0xc0, 0xc0, 0xe0, 0xe0, 0xe0, 0xf0, 0xf0, 0xf0, 0xf8, 0xf8, 0xf8, 0xf8, 0x7c, 0xfc, 0xfc, 0xfc,
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0xfc, 0xfc, 0xfc, 0x7c, 0x7e, 0x7e, 0x7e, 0x7c, 0x7c, 0x7c, 0x7c, 0xfc, 0xfc, 0xf8, 0xf8, 0xf0,
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0xf0, 0xe0, 0xc0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xc0, 0xc0, 0xe0, 0xe0,
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0xe0, 0xc0, 0x80, 0x20, 0x10, 0x10, 0x18, 0x08, 0x0c, 0x0e, 0x06, 0x07, 0x7f, 0x7f, 0x3f, 0x3f,
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0x1f, 0x0f, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x7f, 0x3f,
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0x3f, 0x1f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x01, 0x01, 0x01, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x80, 0xc0, 0xf0, 0xf8, 0xfc, 0xfe, 0xfe, 0xff, 0x7f, 0x3f, 0x0f, 0x07, 0x07,
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0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xf0, 0xf8, 0xf8, 0xfc,
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0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf8, 0xf8,
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0xfc, 0xfe, 0xfe, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xc0, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc,
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0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xc0, 0xf8, 0xfc, 0xfc, 0xfc, 0xc0, 0xc0, 0xc0,
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0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x03, 0x0f, 0x1f, 0x3f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfc,
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0xf8, 0xe0, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x3f, 0x3f, 0x3f, 0x1f,
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0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x1f, 0x3f, 0x3f, 0x3f, 0x03, 0x03, 0x03,
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0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x0f, 0x7f, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xe0, 0xfc, 0xff, 0xff, 0xff, 0xff,
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0xff, 0x7f, 0x1f, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x07, 0x07,
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0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
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0x00, 0x00, 0x00, 0x00, 0x20, 0x30, 0x3c, 0x3e, 0x3f, 0x3f, 0x1f, 0x0f, 0x07, 0x07, 0x03, 0x01,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x01,
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0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
|
||||
oled.write_data(bitmapSII)
|
||||
|
||||
|
||||
class FoursNeoPixel():
|
||||
def __init__(self, pin_number):
|
||||
self._pin = pin_number
|
||||
self._max_leds = 4
|
||||
self._leds = neopixel.NeoPixel(self._pin, 4)
|
||||
|
||||
def set_led(self, addr, red, green, blue):
|
||||
if addr >= 0 and addr < self._max_leds:
|
||||
# coded on BGR
|
||||
self._leds[addr] = (blue, green, red)
|
||||
|
||||
def set_led2(self, addr, rgb):
|
||||
if addr >= 0 and addr < self._max_leds:
|
||||
# coded on BGR
|
||||
self._leds[addr] = rgb
|
||||
def show(self):
|
||||
self._leds.write()
|
||||
def clear(self):
|
||||
for i in range (0, self._max_leds):
|
||||
self.set_led(i, 0,0,0)
|
||||
self.show()
|
||||
leds = FoursNeoPixel(alphabot.pin_RGB)
|
||||
|
||||
|
||||
|
||||
def motorCallback(motG, motD):
|
||||
@ -28,14 +119,22 @@ def motorCallback(motG, motD):
|
||||
sMotD = 1 - ((motD >> 2) & 0b10)
|
||||
motG = ((motG & 0b0111) * sMotG) * motorSpeedFactor / 7
|
||||
motD = (((motD & 0b0111) * sMotD) * motorSpeedFactor / 7) * motorDCompensation
|
||||
print("Mot G :", motG)
|
||||
print("Mot D :", motD)
|
||||
# print("Mot G :", motG)
|
||||
# print("Mot D :", motD)
|
||||
alphabot.setMotors(left=motG, right=motD)
|
||||
|
||||
def registerCallback(register, value):
|
||||
print(f"Register R{register} changed to {value}")
|
||||
pass
|
||||
|
||||
global leds
|
||||
# print(f"Register R{register} changed to {value}")
|
||||
if (register == 0):
|
||||
leds.set_led(0, value, abs(127 - value), 255 - value)
|
||||
elif (register == 1):
|
||||
leds.set_led(1, value, abs(127 - value), 255 - value)
|
||||
elif (register == 2):
|
||||
leds.set_led(2, value, abs(127 - value), 255 - value)
|
||||
else:
|
||||
leds.set_led(3, value, abs(127 - value), 255 - value)
|
||||
leds.show()
|
||||
|
||||
|
||||
# to know COM port used when connected on PC:
|
||||
@ -48,14 +147,30 @@ robotName = 'Nogard'
|
||||
toSend = []
|
||||
|
||||
def onMsgToRobot(data:str|bytes):
|
||||
global useLED, useMotor
|
||||
if (not ("useLED" in globals())):
|
||||
useLED = False
|
||||
if (not ("useMotor" in globals())):
|
||||
useMotor = True
|
||||
"""Function to call when a message sent by PC is received
|
||||
:param data: message received"""
|
||||
checksum = binascii.crc32(data)
|
||||
print('received', data, '=>', checksum)
|
||||
print(data)
|
||||
|
||||
StartCPU(data, motorCallback, registerCallback)
|
||||
alphabot.stop()
|
||||
if (data[0] == "#"):
|
||||
data = data[1:]
|
||||
if (data == "LED ON"):
|
||||
useLED = True
|
||||
elif (data == "LED OFF"):
|
||||
useLED = False
|
||||
elif (data == "MOTOR ON"):
|
||||
useMotor = True
|
||||
elif (data == "MOTOR OFF"):
|
||||
useMotor = False
|
||||
else:
|
||||
StartCPU(data, motorCallback if useMotor else None, registerCallback if useLED else None)
|
||||
alphabot.stop()
|
||||
|
||||
|
||||
async def robotMainTask(bleConnection):
|
||||
|
||||
23
notes.txt
23
notes.txt
@ -153,19 +153,24 @@ TIM valeur ;génération binaire 11111000 mvvvvvvv
|
||||
|
||||
|
||||
|
||||
1000ms = 85cm (vitesse 3)
|
||||
toupie 76 100ms = 360 + 90°
|
||||
|
||||
42
|
||||
76
|
||||
|
||||
|
||||
Connexion
|
||||
{"type": "connect", "name": "Nogard"}
|
||||
|
||||
{"type": "msg", "format": "base64", "string": "4Dvw+IKA"}
|
||||
Commandes annexes
|
||||
{"type": "msg", "format": "str", "string": "#LED ON"}
|
||||
{"type": "msg", "format": "str", "string": "#LED OFF"}
|
||||
{"type": "msg", "format": "str", "string": "#MOTOR ON"}
|
||||
{"type": "msg", "format": "str", "string": "#MOTOR OFF"}
|
||||
|
||||
Demi tour
|
||||
{"type": "msg", "format": "base64", "string": "4Dvw+IHgAPCA"}
|
||||
Fibbo 8bits
|
||||
{"type": "msg", "format": "base64", "string": "4ADhAfDx4gBc2d5RVzTAEkAF4EGA"}
|
||||
|
||||
Fibbo 16bits
|
||||
{"type": "msg", "format": "base64", "string": "4AHV2t/y8/LzoKGh1dbRYTLAFUAXE/+g0NPUYDfAIUAjQCdjYkAHY2KA"}
|
||||
|
||||
LED
|
||||
{"type": "msg", "format": "base64", "string": "0NXa3xD1+AGQ3MAEEfX4AZHcwAwS9fgBktzAFBP1+AGT3MAcgA=="}
|
||||
|
||||
Demi tour + fuite
|
||||
{"type": "msg", "format": "base64", "string": "4Dvw+ID4MuAA8Phk4Mzw+KXgAPDgAPD4ZIA="}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user